This book presents an overview of the issues related to the test, diagnosis and fault-tolerance of Network on Chip-based systems. It is the first book dedicated to the quality aspects of NoC-based systems and will serve as an invaluable reference to the problems, challenges, solutions, and trade-offs related to designing and implementing state-of-the-art, on-chip communication architectures.
This book first presents the characteristics of the NoC design (topologies, structures, routers, wrappers, and protocols), as well as a summary of the terms used in the field and an overview of the existing industrial and academic NoCs. Secondly, the main aspects of the test of a NoC-based system are discussed, starting with the test of the embedded cores where the NoC plays an important role. Current test strategies are presented, such as the reuse of the network for core testing, test scheduling for the NoC reuse, test access methods and interface, efficient reuse of the network, and power-aware and thermal aware NoC-based SoC testing. Then, the challenges and solutions for the NoC infrastructure (interconnects, routers, and network interface) test and diagnosis are presented. Finally, fault tolerance techniques for the NoC are discussed, including techniques based on error control coding, retransmission, fault location, and system reconfiguration.
Provides state-of-the-art research on the challenges to test, diagnose and tolerate faults in NoC-based systems;
Includes numerous, current test strategies, including re-use of the network for core testing, test scheduling for the NoC reuse, test access methods and interface, efficient re-use of the network, and power-aware and thermal-aware NoC-based SoC testing;
Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings.
